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Je vais ouvrir un post dédié car cela sera utile en dehors de ce projet.
Bonjour.
Assemblage PCB:
Juste pour vous informer que je viens de faire une simulation pour un double face et les prix ont fortement augmenté chez JLCPCB.
Pour ma part, je ne ferai plus que des simples faces....
Alors pour un quatre couches……
#include <ccl.h>
/**
* \brief Initialize CCL peripheral
* \return Return value 0 if success
*/
int8_t DIGITAL_GLUE_LOGIC_0_init()
{
// CCL.SEQCTRL0 = CCL_SEQSEL_DISABLE_gc; /* Sequential logic disabled */
// CCL.SEQCTRL1 = CCL_SEQSEL_DISABLE_gc; /* Sequential logic disabled */
CCL.TRUTH0 = 4; /* Truth 0: 4 */
// CCL.LUT0CTRLC = CCL_INSEL2_MASK_gc; /* Masked input */
CCL.LUT0CTRLB = CCL_INSEL0_AC0_gc /* AC0 OUT input source */
| CCL_INSEL1_IN1_gc; /* IO pin LUTn-IN1 input source */
CCL.LUT0CTRLA = CCL_CLKSRC_CLKPER_gc /* Peripheral Clock */
| CCL_EDGEDET_DIS_gc /* Edge detector is disabled */
| CCL_FILTSEL_DISABLE_gc /* Filter disabled */
| 1 << CCL_ENABLE_bp /* LUT Enable: enabled */
| 1 << CCL_OUTEN_bp; /* Output Enable: enabled */
CCL.TRUTH1 = 1; /* Truth 1: 1 */
CCL.LUT1CTRLC = CCL_INSEL2_EVENTB_gc; /* Event input source B */
CCL.LUT1CTRLB = CCL_INSEL0_AC0_gc /* AC0 OUT input source */
| CCL_INSEL1_EVENTA_gc; /* Event input source A */
CCL.LUT1CTRLA = CCL_CLKSRC_CLKPER_gc /* Peripheral Clock */
| CCL_FILTSEL_DISABLE_gc /* Filter disabled */
| 1 << CCL_ENABLE_bp /* LUT Enable: enabled */
| 1 << CCL_OUTEN_bp; /* Output Enable: enabled */
CCL.TRUTH2 = 4; /* Truth 2: 4 */
CCL.LUT2CTRLC = CCL_INSEL2_IN2_gc; /* IO pin LUTn-IN2 input source */
CCL.LUT2CTRLB = CCL_INSEL0_AC0_gc /* AC0 OUT input source */
| CCL_INSEL1_IN1_gc; /* IO pin LUTn-IN1 input source */
CCL.LUT2CTRLA = CCL_CLKSRC_CLKPER_gc /* Peripheral Clock */
| CCL_EDGEDET_DIS_gc /* Edge detector is disabled */
| CCL_FILTSEL_DISABLE_gc /* Filter disabled */
| 1 << CCL_ENABLE_bp /* LUT Enable: enabled */
| 0 << CCL_OUTEN_bp; /* Output Enable: disabled */
CCL.TRUTH3 = 4; /* Truth 3: 4 */
CCL.LUT3CTRLC = CCL_INSEL2_EVENTB_gc; /* Event input source B */
CCL.LUT3CTRLB = CCL_INSEL0_AC0_gc /* AC0 OUT input source */
| CCL_INSEL1_EVENTA_gc; /* Event input source A */
CCL.LUT3CTRLA = CCL_CLKSRC_CLKPER_gc /* Peripheral Clock */
| CCL_EDGEDET_DIS_gc /* Edge detector is disabled */
| CCL_FILTSEL_DISABLE_gc /* Filter disabled */
| 1 << CCL_ENABLE_bp /* LUT Enable: enabled */
| 0 << CCL_OUTEN_bp; /* Output Enable: disabled */
CCL.CTRLA = 1 << CCL_ENABLE_bp /* Enable: enabled */
| 0 << CCL_RUNSTDBY_bp; /* Run in Standby: disabled */
// CCL.INTCTRL0 = CCL_INTMODE0_BOTH_gc /* Sense both edges */
// | CCL_INTMODE1_BOTH_gc /* Sense both edges */
// | CCL_INTMODE2_BOTH_gc /* Sense both edges */
// | CCL_INTMODE3_BOTH_gc; /* Sense both edges */
return 0;
}
#include "Logic.h"
#include "Event.h"
//PIN_PB0 PIN_PB1 and PIN_PB3 are mapped by default on LOGIC BLOCK CCL LUT2
void INIT_LOGIC_BLOCK2()
{
Logic2.enable; //ENABLE LUT2
Logic2.input0 = logic::in::input; //input PIN_PB0
//Logic2.input1 = logic::in::input; //input PIN_PB11
Logic2.input1 = logic::in::event_a; //event_a OF LUT2
Logic2.input2 = logic::in::masked; //masked = not used
//Logic2.output = logic::out::enable; //active output
Logic2.output = logic::out::disable; //disable output
//Logic2.output_swap = logic::out::no_swap; // Use position, pin 3 on the port so here PIN_PB3
//Logic2.output_swap = logic::out::pin_swap; // Use alternative position, pin 6 on the port so here PIN_PB6
Logic2.truth = 0x08; //AND OUT ON IF BOTH IN ARE HIGH
Logic2.init();
Logic2.start();
}
void INIT_EVENT()
{
Event0.assign_generator_pin(gen0::pin_pa1);
Event0.set_user(user::ccl2_event_a); //EVENT A OF LUT2
Event0.start();
Event1.assign_generator(gen::ccl2_out);
//Event1.set_user_pin(user::evouta_pin_pa2); //route on PA2
Event1.set_user_pin(user::evouta_pin_pa7); //route on PA7
Event1.start();
}
Logic2.output = logic::out::enable; //enable OUTPUT PIN le routage se fait sur la broche par défaut soit PIN_PA3 ( la librairie met par défaut la broche usuelleLogic2.output_swap = logic::out::no_swap; //use PIN_PA3 as OUTPUT for LUT2
Logic2.output = logic::out::enable; //active OUTPUT
Logic2.output_swap = logic::out::pin_swap; // Use alternative position, pin 6 on the port so here PIN_PB6
#include "Logic.h"
#include "Event.h"
//PIN_PB0 PIN_PB1 and PIN_PB3 are mapped by default on LOGIC BLOCK CCL LUT2
void INIT_LOGIC_BLOCK2()
{
Logic2.enable; //ENABLE LUT2
Logic2.input0 = logic::in::input; //input PIN_PB0
//Logic2.input1 = logic::in::input; //input PIN_PB11
Logic2.input1 = logic::in::event_a; //event_a OF LUT2
Logic2.input2 = logic::in::masked; //masked = not used
Logic2.output = logic::out::enable; //active output
//Logic2.output_swap = logic::out::no_swap; // Use position, pin 3 on the port so here PIN_PB3
Logic2.output_swap = logic::out::pin_swap; // Use alternative position, pin 6 on the port so here PIN_PB6
Logic2.truth = 0x08; //AND OUT ON IF BOTH IN ARE HIGH
Logic2.init();
Logic2.start();
}
void INIT_EVENT()
{
Event0.assign_generator_pin(gen0::pin_pa1);
Event0.Event3.set_user(user::ccl2_event_a); //EVENT A OF LUT2
Event0.start();
}
void setup() {
PORTA.DIRCLR = PIN1_bm; //INPUT for PIN_PA1 = pinMode(PIN_PA1,INPUT) but faster!!
INIT_EVENT();
INIT_LOGIC_BLOCK2();
}
void loop() {
}
#include "Logic.h"
#include "Event.h"
//PIN_PB0 PIN_PB1 and PIN_PB3 are mapped by default on LOGIC BLOCK CCL LUT2
void INIT_LOGIC_BLOCK2()
{
Logic2.enable; //ENABLE LUT2
Logic2.input0 = logic::in::input; //input PIN_PB0
//Logic2.input1 = logic::in::input; //input PIN_PB1
Logic2.input1 = logic::in::event_a; //event_a OF LUT2
Logic2.input2 = logic::in::masked; //masked = not used
Logic2.output = logic::out::enable; //enable OUTPUT
Logic2.output_swap = logic::out::no_swap; //use PIN_PA3
Logic2.truth = 0x08; //AND OUT ON IF BOTH IN ARE HIGH
Logic2.init();
Logic2.start();
}
void INIT_EVENT()
{
Event0.assign_generator_pin(gen0::pin_pa1);
Event0.set_user(user::ccl2_event_a); //EVENT A OF LUT2
Event0.start();
}
void setup() {
PORTA.DIRCLR = PIN1_bm; //INPUT for PIN_PA1 = pinMode(PIN_PA1,INPUT) but faster!!
INIT_EVENT();
INIT_LOGIC_BLOCK2();
}
void loop() {
}